Course Code : CS-64
Course Title : Introduction to Computer Organisation
Assignment Number : BCA (4)-64/Assignment/ 2008
Maximum Marks : 25
Last Date of Submission : 30th April, 2008/30th October, 2008

Question 1:-
i) convert the hexadicimal number ABCDEF to binary and octal.
ii) Perform the arithmatic operation (+28)+(-15) in binary using signed -2's complement representation for nagative numbers.
iii) Compare the static RAM and Dynamic RAM.
iv) Explain DMA controller with the help of a block diagram. What is meant by a block transfer ?
v) What is the difference between memory mapped Input / Output and peripheral mappaed Input / Output.

i) First conversion of Hexadecimal number to binary number.
Each digits has a binary representation using four bits.
A = 1010
B = 1011
C = 1100
D = 1101
E = 1110
F = 1111
      For conversion to binary just put the bits next to each other
ABCDEF becomes

      Now conversion of Hexadecimal to octal number
Each digits has a octal representation
A = 12
B = 13
C = 14
D = 15
E = 16
F = 17
      For conversion to octal just put the bits next to each other.

ii) Perform the arithmetic operation (+28)+(-15) in binary using signed -2's complement representation for negative numbers.

        Signed value of (28) is    00111000
        Signed value of (-15) is  10011110
        Sum of the no. are           10010110

iii) Compare the static RAM with Dunamic RAM.

SRAM (static RAM). This type of memory maintains data in storage as long as it is powered. Because it is faster and more reliable and expensive than DRAM, SRAM is most often used as cache memory. Earlier forms of SRAM were classified as Async or Sync RAM if they were synchronized with the system clock. The most common type of SRAM today is pipeline burst SRAM, which can operate at higher bus speeds.

DRAM (dynamic RAM).
This type of RAM retains its data by being continuously rewritten every few milliseconds. Like SRAM, the data in storage is volatile, meaning it is lost when the system is not powered. DRAM is the most common type of expandable company memory in workstations and servers today, but there are several different types of DRAM. 

Explain DMA controller with the help of a block diagram. What is meant by a block transfer?

Ans:- In DMA as the name suggest the memory can be accessed directly by i/o module. Thus overcome the drawback of programmed i/o and interrupt driven i/o where the CPU is responsible for extracting data from the memory for output & storing data in memory for input. DMA provids different information.
i) which operation (read/write) to be performed.
ii) The address of i/o device which is to be used.
block transfer
The process, initiated by a single action of transferring one or more block of data.

Question 2:-
i) Draw the 8086's internal configuration and explain the operation of its components.
ii) What are the advantages of using segment registers in the 8086 microprocessor?
iii) List the unconditional branch instructions in 8086 with example and explain.


For original fig search on block-3 page-10 (fig.3)

The 8086 CPU is divided into two independent functional units (Please refer to the above fig.)
1. The Bus Interface Unit, and
2. The Execution unit.

These two units function in parallel, thereby increasing the processing speed of the CPU,
1.Bus Interface unit :
            The bus interface unit is the 8086's interface to the outside world. It provides a full 16-bit bidrectional data bus and 20-bit address. The bus interface unit is responsible for performing all external bus operations. Specially, it has the following functions :
                        instruction fetch
                        instruction queueing
                       operation fetch and storage
                        address relocation
                        bus control
The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write. These signals are needed for control of the circuits in the memory and I/O systems.
2.Execution Unit :
            The execution unit is responsible for decoding and executing all instructions. It consists of an ALU, status and control flags, eights general-purpose registers, temporary registers, and queue control logic.
            The EU extracts instructions from the top of the queue in the BIU, decods then, generates operand addresses if necessary, passes them to BIU and request it to perform the read or write bus cycles to memory or I/O, and performs the operations specified by the instruction on the operands. During execution of the instruction, EU tests the status and control flags and update them based on the results of executing the instruction. If the queue is empty, the EU waits for the next instruction byte to fetched and shifted to the top of the queue.
            When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

Register Set :
            The 8086 has four groups of user-accessible interval registers. They are
                        instruction pointer
                        four data registers
                        four pointer and index registers
                        four segment registers.
            They represent a total of thirteen 16-bit registers. In addition to these registers, there is another 16-bit register called the status register, with 9 of its bits implemented for status and control flags.

ii) Segment registers are used for accessing the segments. 8086 microprocessor organiges the momory as segment of sizes64Kb size. These segments are organized into four groups :
-- Code segment
-- Data segment
-- Stack segment
-- Extra segment
The segments code, data, stack and extra are pointed by the registers CS, DS, SS and ES respectively.
These registers are located in bus Interface Unit(BIU) of 8086 microprocessor.
These registers are used to store the 6-bit starting address of the four memory segment. This BIU generates 20 bit address using the address and the off set component of the address.
Hence physical address of 20 bit is generated by using starting address :- offset Combination.

Question 3:-
i) Design a 16bit bus using registers and multiplexers and expalin its operations.
ii) Represent the number (64.6)10 as a floating point binary number with 24 bits. The normalized fraction mantissa has 16bits and the exponents has 8bits.
iii) Design a BCD counter that counts 0 to 0, 0000, 0001...1001, 0000. Explain its operation by means of a fourth table.



Question 4:-
i) Write a program in 8086 assembly language to add two 16 digit packed BCD numbers.

Data segment source str db 51h,21h,20h,33h,40h,45h,32h,35h.
dest_str db //dub 35h”$”
Data ends
Code segment
Assume cs:code ,data:data
Packed nbcd 51h,23h,25h.
ASCII values 35h,31h,32h,33h,35h.
Start :
Mov ax ,data
Mov ds ,dx
Mov si offset source_str
Mov si offset dest _str
 Mov ex_oah
Loop start :
Mov al [sj]
Mov bl ,al
Str al ,4
Add al,30h
Mov dest,of h 
Add b1 ,30h
Int d1
Movdest _str[d1],bl
Loop loop start
Code ends
End start

ii) write a program in 8086 assembly language to do conversion of a 16 digit unpacked BCD number to a packed BCD number.

Data segment 
Value 1 db 15h
Value 2 db 10h
Data ends
Code segment
Assume cs: code,ds: data
Mov ax data
Mov ds ax
Mov al,value 1
Xchg value 2 ,al
Mov ax 4c ool
Int 21l

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